`default_nettype none

module clk_even_div_m #(
    parameter [31:0] DIV_DIV_2_CP_I = 1
) (
    input rst_w_ni,
    input clk_w_i,

    output clk_w_o
);
    localparam [31:0] MAX_COUNT_CP_L = DIV_DIV_2_CP_I - 1;
    localparam [31:0] WIDTH_CP_L = $clog2(DIV_DIV_2_CP_I);

    wire [WIDTH_CP_L-1:0] set_count_wp_l;
    wire [WIDTH_CP_L-1:0] get_count_wp_l;
    wire set_clk_w_l;
    assign {set_count_wp_l, set_clk_w_l} = (get_count_wp_l < MAX_COUNT_CP_L) ?
        {get_count_wp_l + 1, clk_w_o} : {0, ~clk_w_o};

    dreg_m #(
        .WIDTH_CP_I(WIDTH_CP_L + 1),
        .INIT_VALUE_CP_I(0)
    ) dreg_i_l (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(clk_w_i),
        .set_en_w_pi(1),
        .set_wp_i({set_count_wp_l, set_clk_w_l}),

        .get_wp_o({get_count_wp_l, clk_w_o})
    );
endmodule
